The present invention relates to a semiconductor device having a memory region and a method of manufacturing the semiconductor device, and in particular, to a semiconductor device in which a non-volatile memory device formed within the memory region includes two charge accumulation regions for each word gate, and a method of manufacturing the semiconductor device.
One type of non-volatile memory device is called a metal-oxide-nitride-oxide semiconductor (MONOS) type or a silicon-oxide-nitride-oxide-silicon (SONOS) type, wherein a gate insulating layer between a channel region and a control gate is formed of a multi-layer stack of silicon oxide and silicon nitride layers, and charge is trapped in the silicon nitride layer.
A device shown in FIG. 17 is known as an example of this MONOS type of non-volatile memory device (non-patent document by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123).
In this MONOS memory cell 100, a word gate 14 is formed on a semiconductor substrate 10 with a gate insulating layer 12 therebetween. A control gate 20 and a control gate 30 are disposed on either side of the word gate 14, in the shape of side walls. There is an insulating layer 22 between a base portion of the control gate 20 and the semiconductor substrate 10, and a side insulating layer 26 between a side surface of the control gate 20 and the word gate 14. In a similar manner, the insulating layer 22 is also between a base portion of the control gate 30 and the semiconductor substrate 10, and the side insulating layer 26 is also between a side surface of the control gate 30 and the word gate 14.
Impurity layers 16 and 18, which are to form a source region and drain region, are formed in the semiconductor substrate 10 between the opposing control gates 20 and 30 of neighboring memory cells.
In this manner, each memory cell 100 has two MONOS memory elements on the side surfaces of the word gate 14. These two MONOS memory elements can be controlled independently. Thus one memory cell 100 can store two bits of information.